1. Field of the Invention
The present invention relates to a manufacturing method for an integrated semiconductor structure.
2. Description of the Related Art
Although in principle applicable to arbitrary integrated semiconductor structures, the following invention and the underlying problems will be explained with respect to integrated DRAM memory circuits in silicon technology.
US 200510003308 A1 discloses a method for fabricating a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor on a semiconductor substrate with an arrangement of mutually adjacent gate electrode stacks on the semiconductor surface. An insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode stacks. Then the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode stacks, an essentially planar surface being formed. Then, the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is then removed above the contact openings on the semiconductor surface. Finally, the contact opening regions are filled with a conductive material.
EP 0 766 301 A2 discloses a method of forming a self-aligned overlapping bit-line contact comprising the steps of depositing a sacrificial material on a film; patterning said material, said material being a sacrificial fill-in for a bit-line contact stud; depositing an oxide on said material; planarizing said oxide; and etching said material in said film to form a self-allient bit-line contact.